Analog to digital conversions are often implemented using quantizers that sample the input analog signal at a selected sampling frequency (f.sub.S), make a determination whether the input analog signal is higher or lower than a reference signal, and output a high or low voltage depending upon this determination. The reference signal may be a DC or AC voltage. Quantizers for analog to digital conversions with high frequency input signals and sampling frequencies above 1 GHz must be capable of making decisions quickly and reliably. These high sampling and input frequencies, however, create significant problems in achieving the goal of consistent and correct operation of such circuits.
A prior quantizer implementation to achieve high frequency analog to digital conversion is the latching comparator 100 depicted in FIG. 1 (Prior Art). This prior latching comparator 100 includes a preamplifier portion, including transistors 116 and 122, and a latch portion, including transistors 118 and 120. The preamplifier and latch portions are clocked out of phase using the track signal (TRACK) 130 and the latch signal (LATCH) 132. Mode selection circuitry, which includes tracking control circuitry that receives the track signal (TRACK) 130 and latching control circuitry that receives the latch signal (LATCH) 132, determines whether the latching comparator is in a tracking or latching mode. While illustrated as npn bipolar devices, the transistors 118 and 120 could also be pnp bipolar transistors or field effect transistors (FETs).
Looking at the preamplifier portion of this circuitry in more detail, an input signal (V.sub.IN) 106 is applied to bias transistor 116. A reference voltage (V.sub.REF) 124 is connected to bias transistor 122. Resistors 112 and 114 are connected between ground 102 and the collectors of transistors 116 and 122, respectively. The emitters of transistors 116 and 122 are connected together at internal track node 142. Transistor 126, which is the tracking control circuitry, is connected between internal track node 142 and node 140 and has a bias voltage set by the track signal (TRACK) 130. Transistor 136 is connected between node 140 and resistor 138 and has a constant bias voltage set by bias voltage (V.sub.BB) 134. Resistor 138 is connected between the emitter of transistor 136 and the negative supply voltage (V.sub.EE) 104. The transistor 136 and the resistor 138 act as a current source in operation.
Looking at the latch portion of this circuitry in more detail, transistor 128 is connected between node 140 and internal latch node 144. Transistor 128, which is the latching control circuitry, is biased by a latch signal (LATCH) 132. Transistors 118 and 120 are connected with the collector of transistor 118 being connected to the base of transistor 120, the collector of transistor 120 being connected to the base of transistor 118, and the emitters of transistors 118 and 120 being connected together to form internal latch node 144. The output (V.sub.OUT2) 110 is taken from the collectors of transistors 120 and 122, which are connected together. The output (V.sub.OUT1) 108 is taken from the collectors of transistors 118 and 116, which are connected together.
In operation, when the track signal (TRACK) 130 is high and the latch signal (LATCH) 132 is disabled (LATCH=low), the differential preamplifier portion of the circuitry is enabled. In this tracking mode, the differential output voltage of node (V.sub.OU2) 110 minus node (V.sub.OUT1) 108 tracks the input signal (V.sub.IN) 106. When the latch signal (LATCH) 132 goes high and the preamplifier stage is disabled (TRACK=low), the latching portion of the circuitry is enabled. At that point, the differential output voltage of node (V.sub.OUT2) 110 minus node (V.sub.OUT1) 108 will be either high or low. In this latching mode, the cross-coupled latch provided by transistors 118 and 120 establishes a positive feedback loop that amplifies the differential preamplifier output to provide a low or high indication of the input signal (V.sub.IN) 106. The track signal (TRACK) 130 transitions from high to low and back at the desired sampling frequency (f.sub.S). The latch signal (LATCH) is set to be 180 degrees out of phase with respect to the track signal (TRACK) 130. Significantly and disadvantageously, the speed of the resulting latching comparator 100 is limited by the unity current gain frequency (f.sub.T) of the transistors 118 and 120.
This prior latching comparator circuit has various disadvantages including operational problems at high speeds and low input voltages. Thus, it is desirable to improve the performance of this prior latching comparator circuit.